Designed the 16-bit pipelined serial/parallel multiplier by utilizing the MOSIS (TSMC) 0.35 μm CMOS process. The 16-bit Pipelined Serial/Parallel Multiplier is capable of multiplying two 16-bit ...

Designed a 16 bit pipe-lined multiplier using the concept of partial products. DRC check and LVS match were performed. It was designed using cadence spectre with almost equal fall and rise delays.