IEEE

Design of an Efficient 4-Bit Serial Parallel Multiplier using QCA

Abstract: This report provides an effective multi-layer serial-parallel 4-bit multiplier (SPM) using QCA technology. Using a completely used majority gate (MV) and a revised compact and flexible ...
IEEE

FPGA Accelerated High Speed Radix-4 Parallel Multiplier

Abstract: Multiplication is essential in the field of digital systems like DSP, AI and ML. The VLSI field involves the reduction of minimising area, power consumption, delay and improving efficiency.
GitHub

kanakroy13/4-bit-signed-parallel-multiplier-verilog-

This project implements a 4x4 bit array multiplier designed using basic building blocks like AND gates, Half Adders (HA), and Full Adders (FA). It multiplies two 4-bit binary numbers and produces an 8 ...
GitHub

MikhaelMounay/Serial-Parallel-Multiplier-FPGA

This project implements an 8-bit signed Serial-Parallel Multiplier on an FPGA using Verilog. The result is displayed in binary on four 7-segment displays, with scrollable output controlled by ...