NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.

This lab course consists of 6 labs and a final project. The labs go through the ASIC design flow, from RTL through GDS. These labs are now available in two process technologies, the ASAP7 7nm ...

This lab is a (slight) modification of the excelent LibreLane workshop that Leo Moser ran during HeiChips 2025. You will learn how to use and configure LibreLane, debug your design, integrate macros, ...