The need for higher performance applications is driving the requirement for a new age of on-chip communication infrastructure. Increasing the clock frequency no longer addresses this higher ...

Recently I worked with a user who was responsible for verifying an AXI interface. This user was coming from a non-UVM background, but was conversant with SystemVerilog. The user was faced with the ...

The first major challenge directly comes from the limited data. Unlike software engineering tasks, where large-scale public data is abundant, the hardware domain, especially UVM verification, is ...