EDN

Flip-Flop Using CMOS NAND Gates

Using just two NAND or inverter gates its possible to build a D type (or ‘toggle’) flip-flop with a push-button input. At power-up the output of gate N2 is at a logical ‘1’, ensuring that transistor T2 ...
GitHub

CMOS-2-input-NAND-gate

Objective: Design a CMOS two-input NAND gate using Cadence and analyze its performance by calculating the fall time and rise time. NAND Gate: A fundamental digital logic gate that outputs true (logic ...
IEEE

Low power CMOS NAND gate using DVS and mutithreshold CMOS technique

Abstract: In digital and analog circuits, power consumption plays an important role in CMOS device. Due to scale down technology in VLSI circuits the threshold voltage of transistors reduced but ...
GitHub

CMOS-NAND-Gate-Design-

Introduction to Magic VLSI Magic is an open-source VLSI layout tool originally developed by John Ousterhout and his team at UC Berkeley. It is widely used for physical chip layout and runs primarily ...
Electronic Specifier

CMOS gate logic

This post answers the question “What is CMOS gate logic?”. A CMOS gate is a system consisting of a pMOS pull-up network connected to the output 1 (or V DD) and nMOS pull-down network, connected to the ...
Electronic Design

Six MOSFETs, Four Pins Create Two-Input Combo NAND/NOR Gate

This CMOS two-input combination NAND/NOR gate is a three-input, fourpin logic gate. A p-channel enhancementtype MOSFET (Q1) and an n-channel enhancement-type MOSFET (Q4) form one complementary ...
EDN

Rad-Tolerant Positive-NAND Gate

The SN54AC00-SP device contains four independent 2-input positive-NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic. SN54AC00-SP is tolerant to radiation.