EDN

Enhance circuit timing design with programmable clock generators (Part 1 of 2)

For additional ways to reduce EMI through board layout and related techniques, this 4-minute video gives tips and techniques: http://focus.ti.com/lit/ml/sllc324 ...
Design-Reuse

Enhance circuit timing design with programmable clock generators (Part 1 of 2)

As digital systems migrate towards increased integration with higher speeds for complicated signal processing capabilities, timing design has become critical for robust system performance, while ...
EDN

Formal approach eases multiple clock design

Multiple, independent clocks are ubiquitous in system-on-chip (SoC) design. Most SoC devices have multiple interfaces, some following standards that use very different clock frequencies. Many modern ...
Design-Reuse

Ultra Low Power Designs Using Asynchronous Design Techniques (Welcome to the World Without Clocks)

Wire delay is beginning to dominate gate delay in current CMOS technologies. According to Moore’s Law by 2016 CMOS feature size should be on the order of 22 nm with clock frequencies reaching around ...
Electronic Design

It Takes A Super Sleuth To Really Debug Clock-Timing Problems

Today's digital-based systems anchor their reliability and performance on the integrity of their clocking systems. Due to the wide-reaching effect these signals have on system performance, it's ...
Electronic Design

Noise Reduction is Crucial to Mixed-Signal ASIC Design Success (Part 1)

Digital transition switching is the primary cause of noise in mixed-signal devices. Signal noise and immunity to power, ground, and substrate noise all benefit from using differential circuits. Design ...