One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for ...

In today’s digital economy, high-scale applications must perform flawlessly, even during peak demand periods. With modern caching strategies, organizations can deliver high-speed experiences at scale.

This paper presents the architecture of a high performance level 2 cache capable of use with a large class of embedded RISC cpu cores. The cache has a number of novel features including advanced ...