IEEE

Dynamic feedback and biasing for a linear CMOS power amplifier with envelope tracking

Abstract: This paper presents a fully integrated CMOS power amplifier (PA) with a dynamic feedback and gate biasing. The two dynamic circuits improve the linearity and efficiency of the stand-alone PA ...
IEEE

NP dynamic CMOS resurrection with carbon nanotube field effect transistors

Abstract: Low-power, compact, and high-performance NP dynamic CMOS circuits implemented with a 16nm carbon nanotube transistor technology are presented in this paper. The performances of NP dynamic ...
Scientific Research Publishing

Timing-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits ()

The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level transistor sizing ...
INSPIRE

A Method to Achieve High Dynamic Range in a CMOS Image Sensor Using Interleaved Row Readout

We present a readout scheme for CMOS image sensors that can be used to achieve arbitrarily high dynamic range (HDR) in principle. The linear full well capacity (LFWC) in high signal regions was ...
GitHub

8:1MULTIPLEXER USING LOGIC GATES DYNAMIC CMOS LOGIC

AIM: Designing and implementation 8:1 mux using logic gates and dynamic cmos logic using cadence virtuoso. An 8:1 multiplexer is a digital circuit that selects one of eight input signals and forwards ...
Scientific Research Publishing

J. P. Fishburn and A. E. Dunlop, “TILOS: A Posynomial Programming Approach to Transistor Sizing,” International Conference on Computer Aided Design, Delft, 7-10 October ...

ABSTRACT: The advancement in CMOS technology has surpassed the progress in computer aided design tools, creating an avenue for new design optimization flows. This paper presents a design level ...