Electronic Design

FPGAs: Architectural Innovations Open Up New Applications

FPGAs have always offered fast turnaround and on-the-fly reconfigurability, but at a higher unit cost. ASICs have promised a lower unit cost at high volumes, but only if designers can afford the time ...
Semiconductor Engineering

Manycore-FPGA Architecture Employing Novel Duet Adapters To Integrate eFPGAs in a Scalable, Non-Intrusive, Cache-Coherent Manner (Princeton)

A technical paper titled “Duet: Creating Harmony between Processors and Embedded FPGAs” was written by researchers at Princeton University. “The demise of Moore’s Law has led to the rise of hardware ...
Semiconductor Engineering

FPGAs: Automated Framework For Architecture-Space Exploration of Approximate Accelerators

A technical paper titled “autoXFPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems” was published (preprint) by researchers at TU Wien, Brno ...
Circuit Digest

Vicharak’s FPGA Boards Start at 349 Rupees and Scale as You Skill Up

Backing its low-cost positioning, the board relies on a fully open-source toolchain. Also, while not official yet, Akshar ...
New Electronics

Altera lifts the lid on the Hyperflex FPGA architecture

Two years after announcing Stratix 10 SoC FPGAs, Altera has disclosed more details about how the devices – being built on Intel's 14nm TriGate process – achieve the claimed performance. Two years ...
Design-Reuse

Implementing DSP Functions Within FPGAs

Cofer and Harding discuss how to implement DSP functionality, covering when FPGAs are a good fit for DSP algorithm implementation and important design decisions and considerations. Each of these ...
EDN

Xilinx 7 Series FPGAs Slash Power Consumption by 50% and Reach 2 Million Logic Cells on Industry’s First Scalable Architecture

SAN JOSE, Calif., June 21 /PRNewswire/ — Xilinx, Inc. (Nasdaq: XLNX) today announced the industry's first FPGA series that slashes total power consumption by 50 percent and offers industry-leading ...
Design-Reuse

Mapping LMS Adaptive Filter IP Core to Multiplier-Array FPGA Architecture for High Channel-Density VOIP Line Echo Cancellation

The LMS adaptive filter is the main functional block in high channel-density line echo cancellers for VOIP. In this paper, we describe an LMS adaptive FIR filter IP and estimate its performance when ...
Nature

Hardware Architecture for Cryptographic Algorithms on FPGA

Field-Programmable Gate Arrays (FPGAs) have become a popular platform for implementing cryptographic algorithms due to their flexibility and efficiency. Recent research has focused on enhancing the ...