EDN

A tutorial on incremental design using FPGAs from Actel

Regardless of the amount of time and energy FPGA designers invest attempting to create “right-first-time” designs, the functional complexities, performance requirements, and high gate counts of large ...
EDN

A tutorial on tools, techniques, and methodology to improve FPGA designer productivity

What is the biggest factor affecting the productivity of FPGA design cycles? Many designers say achieving timing closure is critical in getting a design to market – and with good reason. Achieving ...
Design-Reuse

A tutorial on tools, techniques, and methodology to improve FPGA designer productivity

What is the biggest factor affecting the productivity of FPGA design cycles? Many designers say achieving timing closure is critical in getting a design to market – and with good reason. Achieving ...
Embedded

How to design an FPGA from scratch

Editor's note: This is a brief excerpt from article on EE Times' Programmable Logic Designline. To read the full article, click here. Sven Andersson's tutorial “How to design an FPGA from scratch” was ...
Design-Reuse

A tutorial on incremental design using FPGAs from Actel

Regardless of the amount of time and energy FPGA designers invest attempting to create "right-first-time" designs, the functional complexities, performance requirements, and high gate counts of large ...