Microchip Technology has added an HLS design workflow, called SmartHLS, to its PolarFire FPGA families to allow C++ algorithms to be directly translated to FPGA-optimised Register Transfer Level (RTL) ...

Altera and Mentor Graphics' Catapult C synthesis group have collaborated to help system architects squeeze the most performance out of the DSP blocks Altera includes in its Cyclone II, Cyclone III, ...

CoDeveloper FPGA design tool allows algorithms to be developed and debugged with existing C/C++ tools. The tool helps identify dataflow bottlenecks, generates debugging visualizations for ...

Like many a decade ago, we were enthusiastic about the prospect of triple-hybrid systems in the datacenter. We were convinced that there was a place for CPUs, for GPUs, and for FPGAs in complex and ...

Field-programmable gate arrays (FPGAs) offer a unique platform for the implementation of high-performance sorting algorithms by combining inherent parallelism with customisable hardware architectures.

FPGAs are finding new applications in the age of artificial intelligence, high-speed wireless communications, medical and life science technology, and in complex chip architectures where they can ...

Forbes contributors publish independent expert analyses and insights. Marco Chiappetta is a technologist who covers semiconductors and AI. AMD is celebrating the 40th anniversary of the Field ...