Semiconductor Engineering

LLMs In The High-Level Synthesis Design Flow

A new technical paper titled “Are LLMs Any Good for High-Level Synthesis?” was published by researchers at University of Arizona. Abstract “The increasing complexity and demand for faster, ...
Semiconductor Engineering

Formal Verification Of Synthesizable C++/SystemC Designs

High-level synthesis (HLS) is a design flow in which design intent is described at a higher level of abstraction than RTL, such as in SystemC/C++ or MATLAB. HLS tools are expected to synthesize this ...
EDN

Synthesis needs to change to serve modern chip design

As EDA tools evolve, the resulting products try to increase automation. Unfortunately, the last great advance was from schematics to language-based design starting with the first synthesis tools in ...
Nature

High-Level Synthesis and Design Space Exploration

High-Level Synthesis (HLS) has emerged as a pivotal technology in the transformation of algorithmic descriptions into efficient hardware designs. Coupled with Design Space Exploration (DSE), HLS ...