EDN

The Challenge of Interface Verification

Designs in every industry segment are built around standard interfaces; you probably can't find a complex chip that does not have some sort of standard interface such as PCI, PCI Express, DDR-SDRAM, ...
Design-Reuse

PC/eSPI interface Verification IP Listing

GIGACOM_PCS_400G Verification IP provides a smart and effective way to verify PCS Features with 400G Speed features. The Verification IP is fully compliant with the latest PCS and Ethernet ... eSPI ...
Design-Reuse

Knowlent Alleviates XAUI Interface Electrical Verification Bottleneck with New Opal XAUI EVP

June 8, 2005 - Santa Clara, California - Knowlent Corporation, a Silicon Valley-based Electronic Design Automation (EDA) and Intellectual Property (IP) startup, today announced that it has added XAUI ...
EDN

‘Divide and conquer’ with verification IP

As design complexity and simulator capacity increase, verification and testbench complexity grow exponentially. Languages such as SystemC and SystemVerilog enable designers to work at a higher level ...