EDN

MIPS debuts new cores, instruction set

SAN JOSE, Calif. — MIPS Technologies Inc. is upgrading two of its cores and introducing a new instruction set architecture. The products aim to expand the company's relatively small presence in 32-bit ...
EDN

MIPS’ new embedded core to add multithread

San Mateo, Calif. — MIPS Technologies Inc. will wield a new competitive weapon in the embedded-processor wars this week, when it introduces hardware multithreading as an optional extension to its ...
GitHub

MIPS Processor Implementation in Verilog

This project focuses on the design and implementation of a MIPS processor using Verilog as part of the Computer Architecture Laboratory. The objective was not only to build processor capable of ...
Design-Reuse

MIPS Technologies Targets Multi-CPU SOC Designs With New 32-Bit Processor Core

Small, Flexible, High-Performance MIPS32 M4K Core Enables SOC Designers to Meet Rapidly Increasing Bandwidth DemandsSAN JOSE, Calif., Embedded Processor Forum, April 29, 2002 MIPS Technologies, Inc.
Yahoo

MIPS Technologies Introduces 64-Bit Multithreaded SMT Core

MIPS Technologies, a company that has produced chips that have previously driven devices like TVs and set-top boxes, announced today its plans to offer the first IP core that combines a 64-bit ...