EDN

Tracking PLL design through the decades, part 2

The desire to integrate more gateshas driven two advances in CMOS-processingtechnology, enabling the integrationof practical inductors in genericCMOS-logic processes. The first, theuse of CMP ...
Electronic Design

Smaller PLL Synthesizers Become Design-Friendlier

Phase-locked-loop (PLL) frequency synthesizers are signal sources often employed in many types of electronic equipment. They show up as clock sources in high-frequency instruments and as local ...
Electronics Weekly

ParthusCeva expands PLL design licensing website

Technology licensing firm ParthusCeva has expanded its website for phase locked loop (PLL) design, adding ‘ready-to-go’ PLLs and support for TSMC’s 0.13µm process. The site, PLLXpert Online, was ...
Design-Reuse

Parthus Technologies Announces a Breakthrough in PLL IP Delivery, Putting Design of Custom Clock Synthesis Cores in the Hands of Digital Designers

Dublin, Ireland - April 23, 2002 - Parthus Technologies (Nasdaq: PRTH, LSE: PRH), a leading provider of semiconductor platform-level intellectual property (IP), today announces the launch of a ...
EDN

PLL design kit features timing models, GDSII physical views

A new design kit enables system-on-chip (SoC) developers to efficiently incorporate clocking IP into their designs with full support for layout, simulation, and timing closure. Perceptia Devices, an ...
Design-Reuse

Selecting PLLs for ASIC Applications Requires Tradeoffs

Phase-Locked Loops (PLLs) are commonly used to perform a variety of clock processing tasks, such as clock frequency multiplication and clock deskewing. PLLs, like many other analog IP macros, come ...