Design-Reuse

Physical Design for Reuse Strategies and Implementation

Techniques for IP reuse have become commonplace in the RTL design world. By contrast, physical design for reuse remains stuck at delivering restrictive “hard IP.†What is holding reuse-design back ...
Semiconductor Engineering

Secure Physical Design Roadmap Enabling End-To-End Trustworthy IC Design Flow

The FICS Research Institute (University of Florida) has published a new research paper titled “Secure Physical Design.” This is the first and most comprehensive research work done in this area that ...
EDN

Physical Design Flow Taps Partition Layout

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.
Electronic Design

What’s Next for Physically Aware DFT?

Why isolated flows negatively impact design schedule and PPA. Benefits of unified DFT, synthesis, and physical design flows. Physical implementation optimization methods for test compression and scan ...
Design-Reuse

Top-down SoC Design Methodology

Deep sub-micron effects complicate design closure for very large designs. Top-down hierarchical design methodology combined with physical prototyping increases design productivity and restores ...
EDN

Startup’s tool set spans logical, physical design

Santa Cruz, Calif. – A tool from startup Silicon Dimensions Inc. is said to help logic engineers approach design closure on block-level designs. The Chip2Nite tool, to be announced this week, provides ...