Semiconductor Engineering

Debug This! How To Simplify Coverage Analysis And Closure

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...
Business Insider

Mentor Graphics Expands Formal Verification's Reach with New Cross-Platform GUI and Apps for Sequential Logic Equivalence Checking and CDC Gate-Level Analysis

WILSONVILLE, Ore., April 20, 2017 /PRNewswire/ -- Mentor, a Siemens business, today announced new formal-based technologies in the Questa Verification Solution that provide RTL designers and ...
EDN

Mentor Graphics Drives Next-Generation, Low-Power Verification with UPF Successive Refinement Methodology

The Unified Power Format (UPF) Successive Refinement Methodology enables the incremental specification and early verification of power management intent. The Questa ® Power Aware Simulation solution ...