Design-Reuse

How High-Level Synthesis Can Raise the Efficiency of Design Reuse

Design reuse and IP-based design are established design practices enabling fast integration of large-scale, high-complexity systems. But while silicon potential keeps improving through node shrinks, ...
Design-Reuse

Mentor Graphics and Calypto Design Systems Announce Customer-Proven Electronic System Level Synthesis and Verification Flow Featuring Catapult C Synthesis and SLEC Sequential ...

WILSONVILLE, Ore., January 14, 2008 – Mentor Graphics Corporation today announced the availability of a new electronic system level (ESL) hardware design and verfication flow featuring Mentor’s ...