GitHub

rookiephysicist/About-Go-To-Femto-V-Tutorials-Blink-to-RISC-V-for-tutorial-on-RISC-V-processo

FemtoRV is a minimalistic RISC-V design, with easy-to-read Verilog sources directly written from the RISC-V specification. The most elementary version (quark), an RV32I core, weights 400 lines of ...
Design-Reuse

Codasip Releases a Major Upgrade of Its Studio Processor Design Toolset with a Tutorial RISC-V core

Munich, Germany – April 13 th, 2021 – Codasip, the leading supplier of processor design solutions and customizable RISC-V processor IP, is pleased to announce the availability of Codasip Studio 9.0 ...