GitHub

blackmonoceros/Combinational-Logic-Functions-and-Sequential-Circuits

1.1 Half Adder To show the operation of a multi-bit adder, we will start with the simplest form, which is a half-adder (Half Adder). Run and test the operation of the following circuit. Place the ...
Embedded

Configuring a PSoC for a DIY oscilliscope/logic analyzer – Part 2

Select between the Combination or Sequential circuit for analysis (Figure 16). Figure 16: Screen to select Combinational or Sequential Circuit Select the number of inputs (max of 3) and number of ...
IEEE

On-chip intrinsic evolution methodology for sequential logic circuit design

Abstract: This paper focuses on the application of Virtual Reconfigurable Circuit (VRC) design methodology and intrinsic evolution for the design of small sequential circuits and their implementation ...
IEEE

Low-Cost Sequential Logic Circuit Design Considering Single Event Double-Node Upsets and Single Event Transients

Abstract: As CMOS device sizes continue to scale down, radiation-related reliability issues are of ever-growing concern. Single event double node upsets (SEDUs) in sequential logic and single event ...