A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz. Simulation of the Tomasulo algorithm using python ...

• Designed a simulator for an out-of-order superscalar processor based on Tomasulo’s algorithm. • Integrated the Instruction Cache with the dynamic instruction scheduler to model the fetch from the ...