TechRepublic

Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine

Viterbi decoder is the dominant module to determining the power consumption of the system. High speed and low power design of Viterbi decoder with data rate1/2 and convolution encoding with a ...
TechRepublic

Performance Analysis of Viterbi Decoder using different Digital Modulation Techniques in AWGN Channel

In this proposed paper, a simulation of convolutional encoder and Viterbi decoder presented. This paper focuses on the performance study of Viterbi algorithm by varying parameters like constraint ...
Design-Reuse

Altera's Latest Viterbi Decoder Core Provides the Industry's Best Performance

SAN JOSE, Calif., Dec. 10 /PRNewswire/ -- Altera Corporation (Nasdaq: ALTR - news) today released a significantly enhanced version of the Viterbi decoder core that ...
Design-Reuse

Unified C-programmable ASIP architecture for multi-standard Viterbi, Turbo and LDPC decoding

This paper describes an ASIP decoder template suitable for multi-standard Viterbi, Turbo and LDPC decoding. We show architecture fitness for WLAN, WiMAX and 3GPPLTE standards, although various other ...
EDN

Crafting a Custom Viterbi Decoder for WLAN Designs

Clearly, wireless LAN (WLAN) systems are a hot topic in the design community. With 802.11b taking off, and 802.11g and 802.11a coming quickly, much attention has been placed on building WLAN access ...