GitHub

krailis/zynq-axi-tutorial

The flow of this tutorial begins with the generation of custom IPs through Vivado HLS 2014.4. We employ a very simple example as our source code. Specifically, an integer is given as input to the HW ...
GitHub

Reconfigurable-Computing/Xilinx-FPGA-PCIe-XDMA-Tutorial

Customer stories Events & webinars Ebooks & reports Business insights GitHub Skills ...
Electronic Specifier

Xilinx ISE Design Suite 12.3 Introduces AMBA 4 AXI4 IP Cores, Enhances PlanAhead Design and Analysis Cockpit, Extends Power Optimization

Xilinx is the first to standardize on the AMBA 4 specification as part of our interconnect strategy to support Plug-and-Play FPGA design. SoC designers who have large investments in AMBA AXI3(TM) and ...
Design-Reuse

Xilinx ISE Design Suite 12.3 Introduces AMBA 4 AXI4 IP Cores, Enhances PlanAhead Design and Analysis Cockpit, Extends Power Optimization

Release of ISE Design Suite 12.3 Begins Roll-Out of IP Supporting AXI4 interfaces for Plug-and-Play FPGA Design SAN JOSE, Calif., Oct 05, 2010 --Xilinx, Inc. (Nasdaq: XLNX) today announced the release ...
EDN

Bridging Xilinx Streaming Video Interface with the AXI4-Stream Protocol

The ARM® core AMBA® specification (version 4.0) AXI interconnect standard includes three Advanced eXtensible Interface version 4 (AXI4) interconnect protocols—AXI4 interconnect, AXI4-Lite protocol, ...