Simulating a VHDL/Verilog code using Modelsim SE.
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Simulating a VHDL/Verilog code using Modelsim SE.
ModelSim is a very popular simulation tool among VHDL/Verilog programmers. In this video I try to show you how to compile and simulate a simple VHDL code. The method is the same even if the codes are in Verilog. I am using the free student version of Modelsim for this. VHDL Tutorial Blog: http://vhdlguru.blogspot.com/ Verilog Tutorial Blog ...
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